Job Description:

• Lead RTL design activities for complex ASIC/SoC development projects.
• Work closely with architecture and verification teams to define micro-architecture and implementation strategies.
• Develop high-quality RTL using Verilog/SystemVerilog.
• Drive block-level design, integration, lint, CDC, and synthesis activities.
• Ensure design quality and timely project execution.
• Debug and resolve design issues during simulation, synthesis, and silicon bring-up stages.
• Collaborate with cross-functional teams including DFT, Physical Design, and Verification.
• Mentor junior engineers and support technical reviews.

Required Skills:

• Strong experience in RTL Design for ASIC/SoC projects.
• Hands-on expertise in Verilog/SystemVerilog.
• Good understanding of AMBA protocols (AXI/AHB/APB).
• Experience with synthesis, lint, CDC, and low-power design methodologies.
• Strong debugging and problem-solving skills.
• Prior team handling or technical leadership experience is preferred.